1. Technical Field
The present invention relates to oscillator circuits and related methods, especially phase locked loops with voltage controlled oscillators.
2. Description of Related Art
Phase-locked loops (“PLLs”) which incorporate voltage-controlled oscillators (“VCOs”) are used in a variety of applications, such as to perform channel selection and associated tuning in frequency-division multiplexed systems for radio, television, cable and satellite broadcast systems. In particular cases, the phase-locked loop may need to maintain the frequency output by a voltage-controlled oscillator (“VCO”) for a very long period of time. In a serial data transmission system which can be implemented in an integrated circuit of a semiconductor element such as a chip, for example, transmission and receiving frequencies may need to remain locked over an entire operating lifetime of the chip.
Problems can cause prior art systems to have difficulty maintaining lock for such a long period of time. Operation of a PLL according to the prior art can be explained with reference to FIG. 1. As seen therein, a first curve 12 marked by a solid line plots a frequency output by a VCO versus a control voltage input to the VCO, the control voltage ranging between VA and VB. The first curve 12 indicates a sample result for a particular frequency band of operation, obtained when the chip incorporating the PLL is operated at relatively high temperature. As seen in FIG. 1, the point 14 at which the PLL locks the output frequency fL of the VCO under such condition results from a control voltage VL which is near the low end VA of the range VA-VB of the control voltage.
A problem arises when the temperature decreases. Curve 22 of FIG. 1 marked by a dashed line indicates a result that can occur when the temperature of the chip decreases from the temperature that was present earlier. At lower temperature, the operating curve 22 shifts upward, such that a control voltage input with a lower value is needed in order for the VCO to output and lock the same output frequency fL as before. However, unfortunately there is no control voltage value on the new operating curve 22 which results in the locked output frequency fL. The required output frequency fL is now too low a frequency to be produced by the VCO at the lower temperature. Point 24 on curve 22 results in a frequency fA which is higher than the required output frequency fL. Now, to be able to produce the required output frequency fL, the PLL must begin a coarse calibration process to test different frequency bands in order to select a new frequency band in which to operate. Such coarse calibration process can take considerable time away from normal operation of the chip. In integrated circuits used for data transmission, congestion or disruption of the flow of data communications can result when the PLL becomes unavailable temporarily in order to perform coarse calibration and re-establish the required output frequency.
FIG. 2 is a block and schematic diagram illustrating a PLL 30 with coarse calibrating circuitry in accordance with the prior art. The VCO 32 includes a linear amplifier LA and a resonator including an LC tank circuit. A reference clock frequency (REFCLK) and a divider setting (% N) set the output frequency fL to be maintained by the VCO 32. In some applications such as for use in an intrasystem or inter-system serial data communications receiver, the PLL is expected to remain locked at a single output frequency fL over the entire lifetime of the PLL and the chip in which it is incorporated. In such case, the settings REFCLK and % N remain fixed throughout the lifetime of the chip. Viewed from left to right in FIG. 2, the PLL incorporates a phase-frequency discriminator PFD which produces an error signal 34 based on the difference between the frequencies of REFCLK and a feedback clock signal FBCLK obtained by dividing the output frequency fL with divider (% N). The error signal, typically in form of pulses, is input to a charge pump QP. The charge pump QP integrates the pulses and outputs a signal which is conditioned by a low-pass filter (LPF) to produce a control voltage CV at the input to the VCO 32. For coarse calibration, the charge pump QP produces a common mode voltage level CMV which is a neutral value of the control voltage.
The common mode voltage CMV and the control voltage CV are input to a coarse calibration circuit 36 which contains first and second comparators CN and CP and a circuit 38 to determine a minimum value CVmin and a maximum value CVmax that the control voltage can reach during operation of the PLL. The output COMPM of Comparator CN is activated when CV falls below CVmin. The output COMPP of Comparator CP is activated when CV rises above CVmax. During a coarse calibration operation, these signals COMPN and COMPP indicate whether the control voltage CV falls below the voltage CVmin, is between CVmin and CVmax, or rises above CVmax.
As further shown in FIG. 2, a PLL logic block 40 controls operation of the PLL by selecting the frequency band of the VCO operation through a band selection signal VBANDSEL<3:0> provided to the LC Tank circuit. During coarse calibration, REFCLK and the % N inputs are established and maintained and the PLL logic 40 sets the LC Tank to a given frequency band, which may be the lowest frequency band for the PLL. The PLL then begins operating at a given control voltage CV, which can be at the low end of its range, i.e., at around CVmin. As the PLL then works to make FBCLK equal to REFCLK, the control voltage CV increases over time by operation of the phase frequency discriminator PFD and the charge pump QP. If COMPP becomes active, indicating that CV exceeds CVmax, the required output frequency fL is not found within the selected frequency band. The PLL logic then selects a different frequency band, typically the next higher frequency band, and then performs the foregoing actions again with such frequency band to determine if the required frequency fL can be attained and locked within that frequency band. On the other hand, if the required frequency fL is achieved and the current control voltage value is not beyond the low end CVmin or high end CVmax of its range, a lock point, i.e., the required output frequency, can be achieved within the currently selected frequency band of the PLL.
However, even when the lock point is detected to be within one of the operating frequency bands of the PLL, coarse calibration operation is not finished yet. The PLL illustrated in FIG. 2 is designed to determine the frequency band for which the final control voltage is nearest to the neutral level (the common mode voltage CMV). Thus, when such lock point is detected, the current value of the control voltage CV is saved by the PLL logic 40, as well as signals representing the current CVmax and CVmin values. After the lock point is detected in one operating frequency band, the PLL is switched to one or more other operating frequency bands and the foregoing actions are repeated to determine whether the lock point is achieved within such other operating frequency bands. When the lock point is detected, the current value of the control voltage CV is again saved by the PLL logic 40, as well as signals representing the current CVmax and CVmin values. When all the frequency bands have been determined in which the lock point is achieved, the PLL logic then selects an operating frequency band for which the lock point is closest to the center of the range between CVmin and CVmax for that operating frequency band. The PLL then begins operating with that selected frequency band and is intended to stay within that selected band.
FIG. 3 is a graph illustrating an example of operation within one frequency band of the PLL described above with respect to FIG. 2. Here, the VCO control voltage CV is expressed as a difference from the common mode voltage CMV. In that case, CV having a value of 0V indicates that CV is equal to CMV. FIG. 3 demonstrates that even though lock is achieved when the control voltage CV is 0 V, lying closest to the center of its range CVmin-CVmax, the PLL 30 still may not be selecting the best frequency band of operation. Due to the nature to the nonlinear function of the LC Tank circuit 32 (FIG. 2), and offsets of the linear amplifier and other components of the PLL such as the coarse calibration circuitry 36, the control voltage CV=0 does not necessarily correspond to the center of the variable oscillation frequency band 50 of the VCO. The output frequency curve 50 shown in FIG. 3 rises more steeply on the right side of the figure than it is on the left. When the control voltage is relatively low, a given change in the control voltage produces a somewhat small change in the oscillation frequency. On the other hand, when the control voltage is relatively high, the oscillation frequency changes by a greater amount. Therefore, at the CV=0V point in FIG. 3, the control voltage is zero and at the center of the range CVmin-CVmax, but it does not result in the frequency fc which is the true center of the operating frequency band. Instead, when the control voltage is zero, the VCO has an output frequency 52 which is closer to the minimum frequency Fmin of the frequency band than it is to the maximum frequency Fmax. Therefore, the VCO output frequency cannot be driven down in frequency from the lock point as far as it can be driven up in frequency from the lock point.